1. Field of the Invention
The invention relates generally to the design and fabrication of semiconductor devices and, more particularly, to the design and fabrication of a metal oxide semiconductor (MOS) device having a dual-metal gate, wherein fabrication of the dual-metal gate is achieved in a manner that abates damage to the dielectric material underlying the gate.
2. Related Art
Semiconductor device technology continues the ineluctable advance into the realm of submicron feature sizes. As a consequence of the reduction in feature sizes, aspects of device design and fabrication that were once ignored, because they gave rise to only second-order effects in long-channel devices, are now significant, and have animated numerous modifications to conventional device design and fabrication techniques. For example, the aggressive scaling of channel length and gate oxide thickness in a conventional MOS transistor exacerbates problems of polysilicon gate depletion, high gate resistance, high gate tunneling leakage current and dopant (i.e., boron) penetration into the channel region of the device. In particular, CMOS technology, which once relied on polysilicon as a gate conductor and silicon dioxide as a gate dielectric, now contemplates the use of dual-metal gate conductors and metal oxide (MeOx) gate dielectrics.
MeOx gate dielectric materials are advantageous because they exhibit a relatively high dielectric constant (K), thereby enabling the deposition of a thicker gate dielectric layer without adversely affecting the physical and electrical characteristics of the deposited dielectric layer. For example, thin oxide films are susceptible to catastrophic breakdowns when stressed by high electric fields. SiO2, in particular, can withstand a maximum electric field of approximately 12 mv/cm. A number of transition metal oxides have been demonstrated to be suitable as a substitute for SiO2 in this application, including, for example, oxides of zirconium, hafnium, aluminum, lanthanum, strontium, titanium and combinations thereof.
In addition to enhancements in the gate dielectric, substantial interest has been engendered in the use of metal gates as an alternative to polysilicon. Metal gates not only obviate gate-depletion and boron-penetration effects, but also provide a significantly lower sheet resistance. In one approach, a monolithic gate structure may be incorporated in a CMOS design. Consonant with this approach, a metal with a work function at approximately the midpoint of the valence and conduction bands of silicon has been employed. However, it has been determined that, given such a value for the metal work function, the resulting device threshold voltage, VT, is too high for tractable channel doping. Channel counter-doping to reduce VT gives rise to other problems, such as degradation in short-channel and turn-off characteristics. A solution, in the form of an integrated, dual-metal gate, has therefore been suggested for use in CMOS design. A CMOS transistor design that is predicated on a MeOx gate dielectric and an integrated dual-metal gate conductor is described below.
FIG.1 is a simplified cross-sectional view of a prior-art CMOS transistor 10 that incorporates a MeOx gate dielectric 11 and an integrated dual-metal gate conductor 12. The CMOS transistor itself includes a pMOS transistor 101 that is typically formed in an n-well (not shown) and an nMOS transistor 102 that is formed in a p-well (not shown). Device designers understand a priori that CMOS transistor 10 also includes trench isolation (not shown in FIG.1) in the substrate to separate pMOS transistor 101 from nMOS transistor 102. Gate dielectric 11 is deposited on the surface of the semiconductor substrate over both the pMOS transistor 101 and the nMOS transistor 102. As suggested above, CMOS transistor 10 also incorporates a dual-metal gate conductor 12 in the form of first metal gate conductor 121 and second metal gate conductor 122. First metal gate conductor 121 is deposited and formed on gate dielectric 11 over pMOS region 101. Second metal gate conductor 122 is deposited over first metal gate conductor 121 and on gate dielectric 11 over nMOS region 102.
As indicated above, and for reasons that will presently be offered, dual-metal gate conductors 121 and 122 are formed from heterotypical metallic materials. Specifically, it has been found that favorable performance is attained when the work function of first metal conductor 121 (formed over pMOS region 101) is close to the valence band of silicon and the work function of the second metal conductor 121 (formed over nMOS region 102) is close to the conduction band of silicon. In practice, it is now relatively well established that, for bulk CMOS at gate lengths below 50 nanometers, two different gate metals with respective work functions within about 0.2 eV of the band edges (conduction and valence) of silicon are indicated. Accordingly, candidates for metal gate conductor 121 include rhenium, iridium, platinum, molybdenum, ruthenium and ruthenium oxide; candidates for metal gate conductor 122 include titanium, vanadium, zirconium, tantalum, aluminum, niobium, and tantalum nitride. It is not to be presumed, however, that the above enumeration is exhaustive, and other metals, alloys or compounds may be, or may be found to be, suitable for use as gate conductors in a dual-metal gate architecture.
In general, an existing process of fabricating the gate structure of CMOS transistor 10 proceeds as depicted elliptically in FIG. 2. Subsequent to the deposition of MeOx gate dielectric 11 on the substrate surface, the first metal gate conductor 121 is deposited, preferably by chemical vapor deposition (CVD) techniques, although other deposition techniques, such as physical vapor deposition (PVD) or atomic layer deposition (ALD), may also be utilized. The first metal material is then photolithographically patterned so that the first metal material over pMOS region 101 is protected with photoresist 21. As is illustrated in FIG. 2, a metal removal etch is then performed so that the first metal material over nMOS region 102 is removed down to dielectric layer 11. In one embodiment, metal removal may be effected with a wet etch in a solution of sulphuric acid, hydrogen peroxide and water. The second metal material is then deposited, resulting in the structure embodied in FIG. 1.
The above process introduces a potential for damage to gate dielectric 11, in the area over nMOS region 102. The vulnerable area of gate dielectric 11 is illustrated as the dashed region 111 in FIG. 2. The etiology of this problem may be appreciated with reference to FIG. 2. First, the area of dielectric layer 11 that covers nMOS region 102 is subjected to two metal deposition steps: initially when the first metal material is deposited and again when the second metal material is deposited. But perhaps more detrimentally, the nMOS portion of gate dielectric 11 is exposed to the metal removal etch process that is applied to selectively remove the first metal material over the nMOS region. The removal of first metal 121 over nMOS region 102 is almost inevitably attended by damage to the exposed gate dielectric.
Although the above process has been demonstrated to be acceptable when certain robust MeOx materials (HfO2, for example) are used as the gate dielectric material, it is predictable that other gate dielectrics will experience damage when subjected to the above-described dual-metal integration process. Accordingly, what is required is a method of fabricating a dual-metal gate device without distress to the MeOx dielectric layer.
Skilled artisans appreciate that elements in Drawings are illustrated for simplicity and clarity and have not (unless so stated in the Description) necessarily been drawn to scale. For example, the dimensions of some elements in the Drawings may be exaggerated relative to other elements to promote and improve understanding of embodiments of the invention.